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MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor 21

Electrical and Thermal Characteristics

Figure 11 provides the test access port timing diagram.

Figure 11. Test Access Port Timing Diagram

5.3 Voltage and Frequency Derating

To reduce the power consumption of the device, these devices support voltage and frequency derating

whereby the core voltage (V

) may be reduced if the reduced maximum processor core frequency

requirements are observed. The supported derated core voltage, resulting maximum processor core

frequency (f

core

), and power consumption are provided in Table 11. Only those parameters in Table 11 are

affected; all other parameter specifications are unaffected.

Table 11. Supported Voltage, Core Frequency, and Power Consumption Derating

Maximum Rated

Core Frequency

(Device Marking)

Supported

Derated Core

Voltage (V

)

Maximum Derated Core

Frequency (f

core

)

Full-Power Mode Power

Consumption

Maximum Typical

1000 1.20 V ±50mV 867 MHz 15.5 W 10.5 W

1267 1065 MHz 18.2 W 12.3 W

1333 1167 MHz 18.1 W 12.3 W

1420 1267 MHz 21.0 W 14.2 W

TCK

TDI, TMS

TDO

Output Data Valid

= Midpoint Voltage (OV

/2)

IXJH

IVJH

JLOV

JLOZ

Input

Data Valid

TDO Output Data Valid

JLOX

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 55 56

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