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MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

34 Freescale Semiconductor

System Design Information

9 System Design Information

This section provides system and thermal design recommendations for successful application of the

MPC7447A.

9.1 Clocks

9.1.1 PLL Configuration

The MPC7447A PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency,

the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL

configuration for the MPC7447A is shown in Table 13 for a set of example frequencies. In this example,

shaded cells represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies

that do not comply with the 1400 MHz column in Table 8. When enabled, dynamic frequency switching

(DFS) also affects the core frequency by halving the bus-to-core multiplier; see Section 9.8.5, “Dynamic

Frequency Switching (DFS),” for more information. Note that when DFS is enabled the resulting core

frequency must meet the minimum core frequency requirements described in Table 8.

Table 13. MPC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts

PLL_

CFG[0:4]

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-

Core

Multiplier

Core-to-

VCO

Multiplier

Bus (SYSCLK) Frequency

MHz

100

MHz

133

MHz

167

MHz

01000 2x

10000 3x

10100 4x

2x 668

(1333)

10110 5x 2x

665

(1333)

835

(1670)

10010 5.5x 2x

732

(1466)

919

(1837)

11010 6x 2x

600

(1200)

798

(1600)

1002

(2004)

01010 6.5x 2x

650

(1300)

865

(1730)

1086

(2171)

00100 7x 2x

700

(1400)

931

(1862)

1169

(2338)

00010 7.5x 2x

623

(1245)

750

(1500)

998

(2000)

1253

(2505)

11000 8x 2x

600

(1200)

664

(1328)

800

(1600)

1064

(2128)

1336

(2672)

1 2 ... 29 30 31 32 33 34 35 36 37 38 39 ... 55 56

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