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MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

2 Freescale Semiconductor

Overview

Figure 1. MPC7448 Block Diagram

Integer

Reservation

Station

Unit 2

Integer

Reservation

Station

Unit 2

Additional Features

• Time Base Counter/Decrementer

• Clock Multiplier

• JTAG/COP Interface

• Thermal/Power Management

• Performance Monitor

• Out-of-Order Issue of AltiVec Instr.

x ÷

FPSCR

+ x ÷

Instruction Unit

Instruction Queue

(12-Word)

96-Bit (3 Instructions)

Reservation

Integer

128-Bit (4 Instructions)

32-Bit

Floating-

Point Unit

64-Bit

Reservation

Load/Store Unit

(EA Calculation)

Finished

32-Bit

(16-Entry)

Tags

32-Kbyte

I Cache

Stores

Load Miss

Vec tor

To u ch

Queue

(3)

VR Issue FPR Issue

Branch Processing Unit

CTR

BTIC (128-Entry)

BHT (2048-Entry)

Fetcher

GPR Issue

(6-Entry/3-Issue) (4-Entry/2-Issue) (2-Entry/1-Issue)

Dispatch

Unit

Data MMU

SRs

(Original)

128-Entry

DBAT Array

DTLB

Vector Touch Engine

32-Bit

L1 Castout

Status

L2 Store Queue (L2SQ)

Vector

FPU

Reservation

Station

Reservation

Station

Reservation

Station

Vector

Integer

Unit 1

Vector

Integer

Unit 2

Vector

Permute

Unit

Line

Ta g s

Block 0 (32-Byte)

Status

Block 1 (32-Byte)

Memory Subsystem

Snoop Push/

Interventions

L1 Castouts

Bus Accumulator

L1 Push

(4)

Unit 2 Unit 1

L1 Load Queue (LLQ)

L1 Load Miss (5)

Cacheable Store Miss (2)

Instruction Fetch (2)

L1 Service

L1 Store Queue

(LSQ)

System Bus Interface

L2 Prefetch (3)

Address Bus Data Bus

Queues

Castout

Bus Store Queue

Push

Load

Queue (11)

Queue (5) /

Queue (6)

The Castout Queue and Push Queue share resources such for a combined total of 6 entries.

The Castout Queue itself is limited to 5 entries, ensuring 1 entry will be available for a push.

1-Mbyte Unified L2 Cache Controller

Notes:

Completion Queue

Completion Unit

Completes up

to three

per clock

instructions

1 2 3 4 5 6 7 ... 59 60

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